ispLEVER Classic 2.0.00.17.20.15 Fitter Report File
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Project Name : bb_learn Project Path : C:\projects\ispMach-learn-verilog Project Fitted on : Sun Jul 29 16:36:31 2018 Device : M4256_96 Package : 144 GLB Input Mux Size : 33 Available Blocks : 16 Speed : -5.8 Part Number : LC4256ZE-5TN144C Source Format : Pure_Verilog_HDL Project 'bb_learn' Fit Successfully! Compilation_Times
Prefit Time 0 secs Load Design Time 0.05 secs Partition Time 0.01 secs Place Time 0.02 secs Route Time 0.00 secs Total Fit Time 00:00:01 Design_Summary
Total Input Pins 1 Total Logic Functions 16 Total Output Pins 8 Total Bidir I/O Pins 0 Total Buried Nodes 8 Total Flip-Flops 8 Total D Flip-Flops 8 Total T Flip-Flops 0 Total Latches 0 Total Product Terms 28 Total Reserved Pins 0 Total Locked Pins 9 Total Locked Nodes 2 Total Unique Output Enables 0 Total Unique Clocks 1 Total Unique Clock Enables 0 Total Unique Resets 1 Total Unique Presets 1 Fmax Logic Levels - Device_Resource_Summary
Device Total Used Not Used Utilization ----------------------------------------------------------------------- Dedicated Pins Clock/Input Pins 4 0 4 --> 0 Input-Only Pins 10 1 9 --> 10 I/O / Enable Pins 2 0 2 --> 0 I/O Pins 94 8 86 --> 8 Logic Functions 256 15 241 --> 5 Input Registers 96 0 96 --> 0 GLB Inputs 576 8 568 --> 1 Logical Product Terms 1280 12 1268 --> 0 Occupied GLBs 16 4 12 --> 25 Macrocells 256 14 242 --> 5 Control Product Terms: GLB Clock/Clock Enables 16 1 15 --> 6 GLB Reset/Presets 16 0 16 --> 0 Macrocell Clocks 256 0 256 --> 0 Macrocell Clock Enables 256 0 256 --> 0 Macrocell Enables 256 0 256 --> 0 Macrocell Resets 256 0 256 --> 0 Macrocell Presets 256 0 256 --> 0 Global Routing Pool 356 6 350 --> 1 GRP from IFB .. 0 .. --> .. (from input signals) .. 0 .. --> .. (from output signals) .. 0 .. --> .. (from bidir signals) .. 0 .. --> .. GRP from MFB .. 6 .. --> .. ---------------------------------------------------------------------- <Note> 1 : The available PT is the product term that has not been used. <Note> 2 : IFB is I/O feedback. <Note> 3 : MFB is macrocell feedback. GLB_Resource_Summary
# of PT --- Fanin --- I/O Input Macrocells Macrocells Logic clusters Unique Shared Total Pins Regs Used Inaccessible available PTs used ------------------------------------------------------------------------------------------- Maximum GLB 36 *(1) 8 -- -- 16 80 16 ------------------------------------------------------------------------------------------- GLB A 0 0 0 0/6 0 0 0 16 0 0 GLB B 0 0 0 0/6 0 0 0 16 0 0 GLB C 0 0 0 0/6 0 1 0 15 0 1 GLB D 0 0 0 0/6 0 0 0 16 0 0 ------------------------------------------------------------------------------------------- GLB E 0 0 0 0/6 0 0 0 16 0 0 GLB F 0 0 0 0/6 0 1 0 15 0 1 GLB G 0 0 0 0/6 0 0 0 16 0 0 GLB H 0 0 0 0/6 0 0 0 16 0 0 ------------------------------------------------------------------------------------------- GLB I 0 6 6 6/6 0 10 0 6 10 10 GLB J 2 0 2 2/6 0 2 0 14 2 2 GLB K 0 0 0 0/6 0 0 0 16 0 0 GLB L 0 0 0 0/6 0 0 0 16 0 0 ------------------------------------------------------------------------------------------- GLB M 0 0 0 0/6 0 0 0 16 0 0 GLB N 0 0 0 0/6 0 0 0 16 0 0 GLB O 0 0 0 0/6 0 0 0 16 0 0 GLB P 0 0 0 0/6 0 0 0 16 0 0 ------------------------------------------------------------------------------------------- TOTALS: 2 6 8 8/96 0 14 0 242 12 14 <Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB. <Note> 2 : Four rightmost columns above reflect last status of the placement process. GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell Clk/CE Rst/Pr | Clock CE Enable Reset Preset ------------------------------------------------------------------------------ Maximum GLB 1 1 16 16 16 16 16 ============================================================================== GLB A 0 0 0 0 0 0 0 GLB B 0 0 0 0 0 0 0 GLB C 0 0 0 0 0 0 0 GLB D 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ GLB E 0 0 0 0 0 0 0 GLB F 0 0 0 0 0 0 0 GLB G 0 0 0 0 0 0 0 GLB H 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ GLB I 1 0 0 0 0 0 0 GLB J 0 0 0 0 0 0 0 GLB K 0 0 0 0 0 0 0 GLB L 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ GLB M 0 0 0 0 0 0 0 GLB N 0 0 0 0 0 0 0 GLB O 0 0 0 0 0 0 0 GLB P 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ <Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB. Optimizer_and_Fitter_Options
Pin Assignment : Yes Group Assignment : No Pin Reservation : No @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : No Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : Yes Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : FMAX Fmax_Logic_Level : 1 D/T Synthesis : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 16 Max. P-Term for Splitting : 80 Max Symbols : 24 @Utilization_options Max. % of Macrocells used : 100 @Usercode (HEX) @IO_Types Default = LVCMOS18 (2) @Output_Slew_Rate Default = FAST (2) @Power Default = HIGH (2) @Pull Default = PULLUP_DOWN (2) @Input_Registers Default = None (2) @Register_Powerup Default = None Device Options: <Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. <Note> 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Buried Signal Lists. OSCTIMER_Summary
OSCTIMER: Pin/Node OSCTIMER Instance Name I1 Dynamic Disable Signal gnd_n_n Timer Reset Signal _dup_gnd_n_n Oscillator Output Clock mfb C-15 A0_OSCOUT Timer Output Clock mfb F-15 clk Oscillator Output Clock Frequency 5.0000 MHz Timer Output Clock Frequency 4.7684 Hz Timer Divider 1048576 Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal| | PG Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name| Enable ----------------------------------------------------------------------------------- 1 | GND | - | | | | | | 2 | TDI | - | | | | | | 3 |VCCIO0 | - | | | | | | 4 | I_O | 0 |C12 | | | | | 5 | I_O | 0 |C10 | | | | | 6 | I_O | 0 |C8 | | | | | 7 | I_O | 0 |C6 | | | | | 8 | I_O | 0 |C4 | | | | | 9 | I_O | 0 |C2 | | | | | 10 |GNDIO0 | - | | | | | | 11 | I_O | 0 |D14 | | | | | 12 | I_O | 0 |D12 | | | | | 13 | I_O | 0 |D10 | | | | | 14 | I_O | 0 |D8 | | | | | 15 | I_O | 0 |D6 | | | | | 16 | I_O | 0 |D4 | | | | | 17 | IN0 | 0 | | | | | | 18 | NC | - | | | | | | 19 |VCCIO0 | - | | | | | | 20 | IN1 | 0 | | | | | | 21 | I_O | 0 |E2 | | | | | 22 | I_O | 0 |E4 | | | | | 23 | I_O | 0 |E6 | | | | | 24 | I_O | 0 |E8 | | | | | 25 | I_O | 0 |E10 | | | | | 26 | I_O | 0 |E12 | | | | | 27 |GNDIO0 | - | | | | | | 28 | I_O | 0 |F2 | | | | | 29 | I_O | 0 |F4 | | | | | 30 | I_O | 0 |F6 | | | | | 31 | I_O | 0 |F8 | | | | | 32 | I_O | 0 |F10 | | | | | 33 | I_O | 0 |F12 | | | | | 34 |VCCIO0 | - | | | | | | 35 | TCK | - | | | | | | 36 | VCC | - | | | | | | 37 | GND | - | | | | | | 38 | IN2 | 0 | | | | | | 39 | I_O | 0 |G12 | | | | | 40 | I_O | 0 |G10 | | | | | 41 | I_O | 0 |G8 | | | | | 42 | I_O | 0 |G6 | | | | | 43 | I_O | 0 |G4 | | | | | 44 | I_O | 0 |G2 | | | | | 45 | IN3 | 0 | | | | | | 46 |GNDIO0 | - | | | | | | 47 |VCCIO0 | - | | | | | | 48 | I_O | 0 |H12 | | | | | 49 | I_O | 0 |H10 | | | | | 50 | I_O | 0 |H8 | | | | | 51 | I_O | 0 |H6 | | | | | 52 | I_O | 0 |H4 | | | | | 53 | I_O | 0 |H2 | | | | | 54 |INCLK1 | 0 | | | | | | 55 |GNDIO1 | - | | | | | | 56 |INCLK2 | 1 | | | | | | 57 | VCC | - | | | | | | 58 | I_O | 1 |I2 | * |LVCMOS33 | Output|nled_7_| 59 | I_O | 1 |I4 | * |LVCMOS33 | Output|nled_6_| 60 | I_O | 1 |I6 | * |LVCMOS33 | Output|nled_5_| 61 | I_O | 1 |I8 | * |LVCMOS33 | Output|nled_4_| 62 | I_O | 1 |I10 | * |LVCMOS33 | Output|nled_3_| 63 | I_O | 1 |I12 | * |LVCMOS33 | Output|nled_2_| 64 |VCCIO1 | - | | | | | | 65 |GNDIO1 | - | | | | | | 66 | I_O | 1 |J2 | | | | | 67 | I_O | 1 |J4 | | | | | 68 | I_O | 1 |J6 | | | | | 69 | I_O | 1 |J8 | | | | | 70 | I_O | 1 |J10 | * |LVCMOS33 | Output|nled_1_| 71 | I_O | 1 |J12 | * |LVCMOS33 | Output|nled_0_| 72 | IN4 | 0 | | * |LVCMOS33 | Input |nrst| 73 | GND | - | | | | | | 74 | TMS | - | | | | | | 75 |VCCIO1 | - | | | | | | 76 | I_O | 1 |K12 | | | | | 77 | I_O | 1 |K10 | | | | | 78 | I_O | 1 |K8 | | | | | 79 | I_O | 1 |K6 | | | | | 80 | I_O | 1 |K4 | | | | | 81 | I_O | 1 |K2 | | | | | 82 |GNDIO1 | - | | | | | | 83 | I_O | 1 |L14 | | | | | 84 | I_O | 1 |L12 | | | | | 85 | I_O | 1 |L10 | | | | | 86 | I_O | 1 |L8 | | | | | 87 | I_O | 1 |L6 | | | | | 88 | I_O | 1 |L4 | | | | | 89 | IN5 | 1 | | | | | | 90 | NC | - | | | | | | 91 |VCCIO1 | - | | | | | | 92 | IN6 | 1 | | | | | | 93 | I_O | 1 |M2 | | | | | 94 | I_O | 1 |M4 | | | | | 95 | I_O | 1 |M6 | | | | | 96 | I_O | 1 |M8 | | | | | 97 | I_O | 1 |M10 | | | | | 98 | I_O | 1 |M12 | | | | | 99 |GNDIO1 | - | | | | | | 100 | I_O | 1 |N2 | | | | | 101 | I_O | 1 |N4 | | | | | 102 | I_O | 1 |N6 | | | | | 103 | I_O | 1 |N8 | | | | | 104 | I_O | 1 |N10 | | | | | 105 | I_O | 1 |N12 | | | | | 106 |VCCIO1 | - | | | | | | 107 | TDO | - | | | | | | 108 | VCC | - | | | | | | 109 | GND | - | | | | | | 110 | IN7 | 1 | | | | | | 111 | I_O | 1 |O12 | | | | | 112 | I_O | 1 |O10 | | | | | 113 | I_O | 1 |O8 | | | | | 114 | I_O | 1 |O6 | | | | | 115 | I_O | 1 |O4 | | | | | 116 | I_O | 1 |O2 | | | | | 117 | IN8 | 1 | | | | | | 118 |GNDIO1 | - | | | | | | 119 |VCCIO1 | - | | | | | | 120 | I_O | 1 |P12 | | | | | 121 | I_O | 1 |P10 | | | | | 122 | I_O | 1 |P8 | | | | | 123 | I_O | 1 |P6 | | | | | 124 | I_O | 1 |P4 | | | | | 125 | I_O/OE| 1 |P2 | | | | | 126 |INCLK3 | 1 | | | | | | 127 |GNDIO0 | - | | | | | | 128 |INCLK0 | 0 | | | | | | 129 | VCC | - | | | | | | 130 | I_O/OE| 0 |A2 | | | | | 131 | I_O | 0 |A4 | | | | | 132 | I_O | 0 |A6 | | | | | 133 | I_O | 0 |A8 | | | | | 134 | I_O | 0 |A10 | | | | | 135 | I_O | 0 |A12 | | | | | 136 |VCCIO0 | - | | | | | | 137 |GNDIO0 | - | | | | | | 138 | I_O | 0 |B2 | | | | | 139 | I_O | 0 |B4 | | | | | 140 | I_O | 0 |B6 | | | | | 141 | I_O | 0 |B8 | | | | | 142 | I_O | 0 |B10 | | | | | 143 | I_O | 0 |B12 | | | | | 144 | IN9 | 0 | | | | | | ----------------------------------------------------------------------------------- <Note> GLB Pad : This notation refers to the GLB I/O pad number in the device. <Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins). <Note> Pin Type : ClkIn : Dedicated input or clock pin CLK : Dedicated clock pin I_O : Input/Output pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected Input_Signal_List
Input Pin Fanout Pin GLB Type Pullup Signal ------------------------------------------------- 72 -- IN ---------------- Off nrst ------------------------------------------------- Output_Signal_List
I C P R P O Output N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal -------------------------------------------------------------------------------- 71 J 1 1 1 1 COM ---------------- Fast Off nled_0_ 70 J 1 - 1 1 COM ---------------- Fast Off nled_1_ 63 I 0 - 1 1 COM ---------------- Fast Off nled_2_ 62 I 0 - 1 1 COM ---------------- Fast Off nled_3_ 61 I 3 - 1 1 DFF * R ---------------- Fast Off nled_4_ 60 I 3 - 1 1 DFF * S ---------------- Fast Off nled_5_ 59 I 3 - 1 1 DFF * S ---------------- Fast Off nled_6_ 58 I 3 - 1 1 DFF * S ---------------- Fast Off nled_7_ -------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Bidir_Signal_List
I C P R P O Bidir N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Buried_Signal_List
I C P R P Node N L Mc R E U C I F Fanout Mc GLB P LL PTs S Type E S P E R P Signal --------------------------------------------------------------------- 15 F 0 - 0 1 COM 2 --------IJ------ _dup_gnd_n_n 3 I 3 - 1 1 DFF * S 1 --------I------- bbs1_dout_0_ 5 I 3 - 1 1 DFF * R 1 --------I------- bbs1_dout_1_ 7 I 3 - 1 1 DFF * R 1 --------I------- bbs1_dout_2_ 12 I 3 - 1 1 DFF * R 1 --------I------- bbs1_dout_3_ 15 F 0 - 0 0 COM 2 --------IJ------ clk 15 C 0 - 0 1 COM ---------------- gnd_n_n --------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation IR = Input register FP = Fast path used OBP = ORP bypass used PostFit_Equations
_dup_gnd_n_n = 0 ; (0 pterm, 0 signal) bbs1_dout_0_.D = bbs1_dout_3_.Q ; (1 pterm, 1 signal) bbs1_dout_0_.C = clk ; (1 pterm, 1 signal) bbs1_dout_0_.AP = !nrst ; (1 pterm, 1 signal) bbs1_dout_1_.D = bbs1_dout_0_.Q ; (1 pterm, 1 signal) bbs1_dout_1_.C = clk ; (1 pterm, 1 signal) bbs1_dout_1_.AR = !nrst ; (1 pterm, 1 signal) bbs1_dout_2_.D = bbs1_dout_1_.Q ; (1 pterm, 1 signal) bbs1_dout_2_.C = clk ; (1 pterm, 1 signal) bbs1_dout_2_.AR = !nrst ; (1 pterm, 1 signal) bbs1_dout_3_.D = bbs1_dout_2_.Q ; (1 pterm, 1 signal) bbs1_dout_3_.C = clk ; (1 pterm, 1 signal) bbs1_dout_3_.AR = !nrst ; (1 pterm, 1 signal) gnd_n_n = 0 ; (0 pterm, 0 signal) nled_0_ = nrst ; (1 pterm, 1 signal) nled_1_ = !clk ; (1 pterm, 1 signal) nled_2_ = 1 ; (1 pterm, 0 signal) nled_3_ = 1 ; (1 pterm, 0 signal) nled_4_.D = !bbs1_dout_3_.Q ; (1 pterm, 1 signal) nled_4_.C = clk ; (1 pterm, 1 signal) nled_4_.AR = !nrst ; (1 pterm, 1 signal) nled_5_.D = !bbs1_dout_0_.Q ; (1 pterm, 1 signal) nled_5_.C = clk ; (1 pterm, 1 signal) nled_5_.AP = !nrst ; (1 pterm, 1 signal) nled_6_.D = !bbs1_dout_1_.Q ; (1 pterm, 1 signal) nled_6_.C = clk ; (1 pterm, 1 signal) nled_6_.AP = !nrst ; (1 pterm, 1 signal) nled_7_.D = !bbs1_dout_2_.Q ; (1 pterm, 1 signal) nled_7_.C = clk ; (1 pterm, 1 signal) nled_7_.AP = !nrst ; (1 pterm, 1 signal)